The present invention relates generally to semiconductor manufacturing and, more particularly, to forming FinFET devices.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 50 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 50 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 50 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the principles of the invention form multiple FinFET devices having an increased effective channel width. A group of channels are formed between the source and drain regions of each FinFET device. These channels increase the effective width of the channel region and, therefore, the current carrying capacity of the FinFET devices.
In accordance with the purpose of this invention as embodied and broadly described herein, a method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.
In another implementation consistent with the present invention, a method of manufacturing a semiconductor device that includes a substrate and a first layer formed on the substrate is provided. The method includes etching the first layer to form a source area and a drain area; filling the source and drain areas with a first material to form source and drain regions; forming a plurality of channels in the first layer between the source region and the drain region; depositing a connector material over the first layer between the source region and the drain region; forming a gate mask over the first layer between the source region and the drain region; removing the connector material in the plurality of channels; depositing a channel material in the plurality of channels; forming a gate dielectric over the channel material; depositing a gate material over the gate dielectric; and patterning and etching the gate material to form at least one gate electrode.
In yet another implementation consistent with the principles of the invention, a method for forming two devices on a substrate having a first layer formed thereon, where the first layer comprises one of an oxide and a nitride, is provided. The method includes forming a source region and a drain region in the first layer for a first device and a second device; forming a plurality of channels for the first device in the first layer between the source region and the drain region; depositing connector material for the first device over the first layer between the source region and the drain region; forming a gate mask for the first device over the first layer between the source region and the drain region; removing the connector material from the plurality of channels; depositing channel material for the first device in the plurality of channels; forming a gate dielectric over the channel material for the first device; depositing a gate material over the gate dielectric for the first device; forming at least one gate electrode from the gate material for the first device; and repeating, for the second device, the forming a plurality of channels, depositing connector material, forming a gate mask, removing the connector material, depositing channel material, forming a gate dielectric, depositing a gate material, and forming at least one gate electrode.